如果去除AD中断,一切别的中断都正常;还有,我们的AD中断都是下载在FLAH,在RAM里面运行。
如果去除AD中断,一切别的中断都正常;还有,我们的AD中断都是下载在FLAH,在RAM里面运行。
做两台2808DSP芯片SPI通信的时候发现一个问题,已知主机DSP的MOSI引脚因为虚焊导致通信异常,检测主机DSP的MOSI上无电平变化,一直是低电平;主机SPI的片选引脚STE和时钟信号引脚CLK检测波形都正常,为什么在从机DSP的MOSI上检测到了占空比接近50%的PWM波?按理说主机DSP没有正常发出波形,为什么会在从机的MOSI引脚上会有PWM波呢,两者之间不是应该通过线路连接,电平变化应该一致啊?ps:此时从机只有接收到时钟和片选信号,从机MISO有波形,但是是错误的波形,导致主从机之间的SPI通讯失败
之前在编写的时候运行还是正常的,加入了SVPWM模块后,就出现了不能使用类型(*)(long)”来初始化的问题,请问该怎么解决?
以下是附件,谢谢!
我用TMS320F28335对一个正弦信号进行采样,频率约为1kHz,正弦信号中的直流偏置为1.65v,通过CCS6.0中的Graph工具看采集的数据波形时,发现连续多个采样信号之间的值相等,整个波形呈现锯齿状,如下图所示(两个图中的数据相同,使用bar模式看的更清楚些),ADC和DMA模块的初始化代码如下:
void pwmset()//EPWM初始化代码
{
EPwm1Regs.TBPRD=50;//4us;
EPwm1Regs.TBCTR=0;
EPwm1Regs.TBPHS.all=0;
EPwm1Regs.TBCTL.bit.FREE_SOFT=1;
EPwm1Regs.TBCTL.bit.CLKDIV=1;//sys/12
EPwm1Regs.TBCTL.bit.HSPCLKDIV=3;
EPwm1Regs.TBCTL.bit.PRDLD=0;
EPwm1Regs.TBCTL.bit.PHSEN=0;
EPwm1Regs.TBCTL.bit.CTRMODE=0;
EPwm1Regs.ETSEL.bit.SOCAEN=1;
EPwm1Regs.ETSEL.bit.SOCASEL=2;
EPwm1Regs.ETSEL.bit.SOCBEN=0;
EPwm1Regs.ETPS.bit.SOCAPRD=1;
}
void adcset()//ADC初始化代码
{
InitAdc();
AdcRegs.ADCTRL1.bit.ACQ_PS=1;//预定标系数=1
AdcRegs.ADCTRL1.bit.CONT_RUN=0;//非连续运行
AdcRegs.ADCTRL1.bit.CPS=1;//ADC模块时钟预分频
AdcRegs.ADCTRL1.bit.SEQ_CASC=1;//SEQ级联模式
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ=0;//
AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
AdcRegs.ADCTRL2.bit.SOC_SEQ1=0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=1;
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1=0;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1=1;
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1=0;
AdcRegs.ADCTRL3.bit.SMODE_SEL=0;
AdcRegs.ADCTRL3.bit.ADCCLKPS=3;//12.5Mh;
AdcRegs.ADCCHSELSEQ1.bit.CONV00=0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01=1;
AdcRegs.ADCCHSELSEQ1.bit.CONV02=2;
AdcRegs.ADCCHSELSEQ1.bit.CONV03=3;
AdcRegs.ADCCHSELSEQ2.bit.CONV04=4;
AdcRegs.ADCCHSELSEQ2.bit.CONV05=5;
AdcRegs.ADCMAXCONV.bit.MAX_CONV2=0x5;
// AdcRegs.ADCMAXCONV.bit.MAX_CONV1=0x0;
}
void dmaset()//DMA初始化代码
{
DMAInitialize();
DMADest=&DMABuf1[0];
DMASource= &AdcMirror.ADCRESULT0;
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(6,1,512);//设置每次Burst的字节数、源地址增量、目标地址增量
DMACH1TransferConfig(511,0,0);//设置每次传送包含多少个Burst、传送完毕发中断,源地址增量、目标地址增量
DMACH1WrapConfig(0,0,0,1);//no use wrap;
EALLOW;
// Set up MODE Register:
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_SEQ1INT; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH1.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disable, tansfer won't stop between bursts
DmaRegs.CH1.MODE.bit.CONTINUOUS = CONT_ENABLE; // Continous enable, channel won't be disabled at the end of transfer
DmaRegs.CH1.MODE.bit.SYNCE = SYNC_DISABLE; // Peripheral sync enable/disable
DmaRegs.CH1.MODE.bit.SYNCSEL = SYNC_SRC; // Sync effects source or destination
DmaRegs.CH1.MODE.bit.OVRINTE = OVRFLOW_DISABLE; // Enable/disable the overflow interrupt
DmaRegs.CH1.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit/32-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH1.MODE.bit.CHINTE = CHINT_ENABLE; // Channel Interrupt to CPU enable(PIE)
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
// Enable DMA CH1 interrupt in PIE
EDIS;
}
我是在epwm的中断里面读取EPwm1Regs.CMPA.half.CMPA和EPwm1Regs.TBCTR的值,然后输出DA用示波器观察,代码如下(中断里面):
comp=EPwm1Regs.CMPA.half.CMPA;
counter11=EPwm1Regs.TBCTR;
DA0= comp/15000;
if(DA0>=0.9999)
DA0=0.9999;
if(DA0<=-0.9999)
DA0=-0.9999;
*DA_ADD0 = DA0 * 2048+2048;
DA1= counter11/15000;
if(DA1>=0.9999)
DA1=0.9999;
if(DA1<=-0.9999)
DA1=-0.9999;
*DA_ADD1 = DA1 * 2048+2048;
但是示波器显示的都是一条直线,教问各位前辈是怎么回事呢
#include "driverlib.h"
#include "device.h"
#include "SFO_V8.h"
自己建立的工程,配置HRPWM,工程包含以上头文件和SFO_v8_fpu_lib_build_c28.lib
编译时报错
unresolved symbol _EPwm1Regs, first referenced in ../SFO_v8_fpu_lib_build_c28.lib<SFO_v7_fpu_lib_build_c28.obj>
看了别人的帖子说是要定义
volatile struct EPWM_REGS *ePWM[PWM_CH] ={ &EPwm1Regs, &EPwm1Regs, &EPwm2Regs, &EPwm3Regs, &EPwm4Regs,
&EPwm5Regs, &EPwm6Regs, &EPwm7Regs, &EPwm8Regs};
但是我的工程使用的C2000ware的函数库,以上定义需要用到F2837xS_epwm.h,这个是外设库(不知道叫啥自己起的名字)的头文件
1.怎么样才能使用函数库正确调用SFO函数?
2.外设库和函数库是否可以混用?
TI给的技术文档如附件,,这个观测模型用的是同步旋转坐标系下的电流模型观测转子磁链幅值,
但是我发现在DSP2812,观测实验室异步电机转子磁链幅值大概是0.8,实际值大约0.9,,比实际值小
。这是怎么回事?有人遇到吗
您好,以下是我设置F28027gpio初始化程序,但是GPIO16,17一直高电平,但是GPIO4就可以设置为低电平,不知道怎么回事呢?
EALLOW;
GpioCtrlRegs.GPAQSEL1.all = 0x0000; // GPIO0-GPIO15 Synch to SYSCLKOUT
GpioCtrlRegs.GPAMUX1.all = 0x0000; // GPIO functionality GPIO16-GPIO31
GpioCtrlRegs.GPAMUX2.all = 0x0000; // GPIO functionality GPIO16-GPIO31
GpioCtrlRegs.GPADIR.all = 0xFFFF; // GPIO0-GPIO31 are GP OUTputs
GpioCtrlRegs.GPAQSEL2.all = 0x0000; // GPIO16-GPIO31 Synch to SYSCLKOUT
GpioDataRegs.GPADAT.all = 0xFFFFFFFF; //GPIO0-GPIO31 initial value are 0
GpioCtrlRegs.GPBMUX1.all = 0x0000; // GPIO functionality GPIO32-GPIO34
GpioCtrlRegs.GPBDIR.all = 0xFFFF; // GPIO32-GPIO34 are OUTputs
GpioCtrlRegs.GPBQSEL1.all = 0x0000; // GPIO32-GPIO34 Synch to SYSCLKOUT
GpioDataRegs.GPBDAT.all = 0xFFFFFFFF; //GPIO0-GPIO31 initial value are 0
GpioCtrlRegs.GPAPUD.all = 0xFFFF; // Pullup's disabled GPIO0-GPIO31
GpioCtrlRegs.GPBPUD.all = 0xFFFF; // Pullup's disabled GPIO32-GPIO34
GpioDataRegs.GPACLEAR.bit.GPIO4 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO16 = 1;
GpioDataRegs.GPACLEAR.bit.GPIO17 = 1;
EDIS;
我在用TMS320F28335中的ADC模块采集一个正弦信号,正弦信号已加入滞留偏执,使得所有值均为正,可是在通过DMA传送到RAM4中时,出现了很严重的锯齿,如图所示,我开始以为是ADC分辨率的问题,可是在我调整信号频率以及信号幅度时,锯齿依然存在,而且没有任何变化,仔细观察发现,锯齿中的每“组”均为16个,图1中的信号频率为1kHz,图2中信号的频率为200Hz,锯齿一直为每组16个,怀疑是DMA与ADC配合的问题,下面附上图示及我的主要代码
#include "DSP2833x_Device.h" // Headerfile Include File
#include "DSP2833x_Examples.h"
#pragma DATA_SECTION(DMABuf1,"DMARAML4");
volatile Uint16 DMABuf1[3072];//512*6
volatile Uint16 *DMADest;
volatile Uint16 *DMASource;
Uint16 jieguo[3][512];
Uint16 i=0,j=0;
void pwmset();
void adcset();
void dmaset();
interrupt void dma_isr();
//interrupt void adcx();
void pwmset()
{
EPwm1Regs.TBPRD=50;//4us;
EPwm1Regs.TBCTR=0;
EPwm1Regs.TBPHS.all=0;
EPwm1Regs.TBCTL.bit.FREE_SOFT=1;
EPwm1Regs.TBCTL.bit.CLKDIV=1;//sys/12
EPwm1Regs.TBCTL.bit.HSPCLKDIV=3;
EPwm1Regs.TBCTL.bit.PRDLD=0;
EPwm1Regs.TBCTL.bit.PHSEN=0;
EPwm1Regs.TBCTL.bit.CTRMODE=0;
EPwm1Regs.ETSEL.bit.SOCAEN=1;
EPwm1Regs.ETSEL.bit.SOCASEL=2;
EPwm1Regs.ETSEL.bit.SOCBEN=0;
EPwm1Regs.ETPS.bit.SOCAPRD=1;
}
void adcset()
{
InitAdc();
AdcRegs.ADCTRL1.bit.ACQ_PS=1;//预定标系数=1
AdcRegs.ADCTRL1.bit.CONT_RUN=0;//非连续运行
AdcRegs.ADCTRL1.bit.CPS=1;//ADC模块时钟预分频
AdcRegs.ADCTRL1.bit.SEQ_CASC=1;//SEQ级联模式
AdcRegs.ADCTRL2.bit.EPWM_SOCB_SEQ=0;//
AdcRegs.ADCTRL2.bit.RST_SEQ1=1;
AdcRegs.ADCTRL2.bit.SOC_SEQ1=0;
AdcRegs.ADCTRL2.bit.INT_ENA_SEQ1=1;
AdcRegs.ADCTRL2.bit.INT_MOD_SEQ1=0;
AdcRegs.ADCTRL2.bit.EPWM_SOCA_SEQ1=1;
AdcRegs.ADCTRL2.bit.EXT_SOC_SEQ1=0;
AdcRegs.ADCTRL3.bit.SMODE_SEL=0;
AdcRegs.ADCTRL3.bit.ADCCLKPS=3;//12.5Mh;
AdcRegs.ADCCHSELSEQ1.bit.CONV00=0;
AdcRegs.ADCCHSELSEQ1.bit.CONV01=1;
AdcRegs.ADCCHSELSEQ1.bit.CONV02=2;
AdcRegs.ADCCHSELSEQ1.bit.CONV03=3;
AdcRegs.ADCCHSELSEQ2.bit.CONV04=4;
AdcRegs.ADCCHSELSEQ2.bit.CONV05=5;
AdcRegs.ADCMAXCONV.bit.MAX_CONV2=0x5;
// AdcRegs.ADCMAXCONV.bit.MAX_CONV1=0x0;
}
void dmaset()
{
DMAInitialize();
DMADest=&DMABuf1[0];
DMASource= &AdcMirror.ADCRESULT0;
DMACH1AddrConfig(DMADest,DMASource);
DMACH1BurstConfig(0x5,1,512);//设置每次Burst的字节数、源地址增量、目标地址增量
DMACH1TransferConfig(511,-5,(-2560+1));//设置每次传送包含多少个Burst、传送完毕发中断,源地址增量、目标地址增量
DMACH1WrapConfig(600,600,600,601);//no use wrap;
EALLOW;
// Set up MODE Register:
DmaRegs.CH1.MODE.bit.PERINTSEL = DMA_SEQ1INT; // Passed DMA channel as peripheral interrupt source
DmaRegs.CH1.MODE.bit.PERINTE = PERINT_ENABLE; // Peripheral interrupt enable
DmaRegs.CH1.MODE.bit.ONESHOT = ONESHOT_DISABLE; // Oneshot disable, tansfer won't stop between bursts
DmaRegs.CH1.MODE.bit.CONTINUOUS = CONT_ENABLE; // Continous enable, channel won't be disabled at the end of transfer
DmaRegs.CH1.MODE.bit.SYNCE = SYNC_DISABLE; // Peripheral sync enable/disable
DmaRegs.CH1.MODE.bit.SYNCSEL = SYNC_SRC; // Sync effects source or destination
DmaRegs.CH1.MODE.bit.OVRINTE = OVRFLOW_DISABLE; // Enable/disable the overflow interrupt
DmaRegs.CH1.MODE.bit.DATASIZE = SIXTEEN_BIT; // 16-bit/32-bit data size transfers
DmaRegs.CH1.MODE.bit.CHINTMODE = CHINT_END; // Generate interrupt to CPU at beginning/end of transfer
DmaRegs.CH1.MODE.bit.CHINTE = CHINT_ENABLE; // Channel Interrupt to CPU enable(PIE)
// Clear any spurious flags:
DmaRegs.CH1.CONTROL.bit.PERINTCLR = 1; // Clear any spurious interrupt flags
DmaRegs.CH1.CONTROL.bit.SYNCCLR = 1; // Clear any spurious sync flags
DmaRegs.CH1.CONTROL.bit.ERRCLR = 1; // Clear any spurious sync error flags
// Initialize PIE vector for CPU interrupt:
// Enable DMA CH1 interrupt in PIE
EDIS;
}
void main()
{
InitSysCtrl();
DINT;
InitPieCtrl();
IER = 0x0000;
IFR = 0x0000;
InitPieVectTable();
EALLOW; // Allow access to EALLOW protected registers
PieVectTable.DINTCH1= &dma_isr;
EDIS;
IER |= M_INT7 ;//DMA Interrupts
PieCtrlRegs.PIEIER7.bit.INTx1=1;//DINTCH1
for(i=0;i<1024;i++)
DMABuf1[i]=i;
for(i=0;i<4000;i++);
pwmset();
adcset();
dmaset();
EINT;
EPwm1Regs.ETSEL.bit.SOCAEN=1;
StartDMACH1();
int temp=0;
while(1)
temp++;
}
interrupt void dma_isr()
{
PieCtrlRegs.PIEACK.bit.ACK7=1;
asm(" ESTOP0");
}
无法连接目标板,在Target Configuration File配置页面的Test Connection之后出现如下结果。
使用的下载器为SEED的XDS510PLUS
Test Connection之后出现以下结果:
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag.exe -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\DOCUME~1\ADMINI~1\LOCALS~1\APPLIC~1\.TI\
4084209646\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'seedjca8990isa.dll'.
The library build date was 'Oct 3 2012'.
The library build time was '21:58:41'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
ffff 5ac3
ffff a53c
ffff 0f0f
ffff 3ca5
ffff c35a
An error occurred while hard opening the controller.
-----[An error has occurred and this utility has aborted]--------------------
This error is generated by TI's USCIF driver or utilities.
The value is '-342' (0xfffffeaa).
The title is 'SC_ERR_HUNG_COMMAND'.
The explanation is:
Failure due to the controller command-finish taking too long.
[End]
直接连reset-command都过不去。不知道哪位可以帮忙解答一下。
另外对比的XSD100的Test Connection结果如下:
[Start]
Execute the command:
%ccs_base%/common/uscif/dbgjtag -f %boarddatafile% -rv -o -F inform,logfile=yes -S pathlength -S integrity
[Result]
-----[Print the board config pathname(s)]------------------------------------
C:\DOCUME~1\ADMINI~1\LOCALS~1\APPLIC~1\.TI\
4084209646\0\0\BrdDat\testBoard.dat
-----[Print the reset-command software log-file]-----------------------------
This utility has selected a 100- or 510-class product.
This utility will load the adapter 'jioserdesusb.dll'.
The library build date was 'Oct 3 2012'.
The library build time was '21:58:41'.
The library package version is '5.0.872.0'.
The library component version is '35.34.40.0'.
The controller does not use a programmable FPGA.
The controller has a version number of '4' (0x00000004).
The controller has an insertion length of '0' (0x00000000).
This utility will attempt to reset the controller.
This utility has successfully reset the controller.
-----[Print the reset-command hardware log-file]-----------------------------
The scan-path will be reset by toggling the JTAG TRST signal.
The controller is the FTDI FT2232 with USB interface.
The link from controller to target is direct (without cable).
The software is configured for FTDI FT2232 features.
The controller cannot monitor the value on the EMU[0] pin.
The controller cannot monitor the value on the EMU[1] pin.
The controller cannot control the timing on output pins.
The controller cannot control the timing on input pins.
The scan-path link-delay has been set to exactly '0' (0x0000).
-----[The log-file for the JTAG TCLK output generated from the PLL]----------
There is no hardware for programming the JTAG TCLK frequency.
-----[Measure the source and frequency of the final JTAG TCLKR input]--------
There is no hardware for measuring the JTAG TCLK frequency.
-----[Perform the standard path-length test on the JTAG IR and DR]-----------
This path-length test uses blocks of 512 32-bit words.
The test for the JTAG IR instruction path-length succeeded.
The JTAG IR instruction path-length is 38 bits.
The test for the JTAG DR bypass path-length succeeded.
The JTAG DR bypass path-length is 1 bits.
-----[Perform the Integrity scan-test on the JTAG IR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG IR Integrity scan-test has succeeded.
-----[Perform the Integrity scan-test on the JTAG DR]------------------------
This test will use blocks of 512 32-bit words.
This test will be applied just once.
Do a test using 0xFFFFFFFF.
Scan tests: 1, skipped: 0, failed: 0
Do a test using 0x00000000.
Scan tests: 2, skipped: 0, failed: 0
Do a test using 0xFE03E0E2.
Scan tests: 3, skipped: 0, failed: 0
Do a test using 0x01FC1F1D.
Scan tests: 4, skipped: 0, failed: 0
Do a test using 0x5533CCAA.
Scan tests: 5, skipped: 0, failed: 0
Do a test using 0xAACC3355.
Scan tests: 6, skipped: 0, failed: 0
All of the values were scanned correctly.
The JTAG DR Integrity scan-test has succeeded.
[End]
BIngo ,SUCCEEDED.
为神马510不行啊不行。
常规编写的函数可以用#pragma CODE_SECTION,使其在RAM中运行;
从.lib文件中调用的函数如何设置,也能使其在RAM中运行?
使用了2812的定时器中断TI中断和T3中断,但是在程序运行过程中会奇怪的进入全比较中断4,但是在程序中全程没有使能全比较中断4,请问各位大神什么原因导致进入全比较中断4??如何解决这个问题?
程序由模板例程修改而来,全选择中断4程序部分是死循环,定时中断难以跳出,是不是哪里设置有问题,求大神帮助!!!!
最近在调试TMS320F28062串口烧录模块,将BootLoader文件编译生成的.hex文件转换为.bin文件,通过SCIA发送到RAM,.bin文件发送完成后,再进行真正的握手,解锁、擦除flash、发送APP文件等步骤。目前出现得问题是,在发送.bin文件的过程中,DSP接收了一部分数据后便不再接收数据,抓取数据可以看到,每发送100个数据,DSP则返回PC同样的数据,.bin文件前边90%多的数据传输都正常,只是到最后几百个字节的时候,PC正常发送,但DSP不会再回复。也没有跳转到EntryPoint位置。
之前没有遇到过这种情况,请大家帮忙分析一下,可能会是什么原因造成的?谢谢!
FOC控制永磁同步电机的时候,在启动之前需要将转子拉到固定位置,比如说是电角度为零的位置,这样做是为了保证转子受力的方向是垂直的。我想问的是假如说一开始不将转子拉到零点,而是拉到-30°位置的话,程序上怎么实施呢?是跟那个斜坡函数有关系吗,我理解的是将斜坡函数的初始角度设为-30°就可以了,然后等到启动之后再将电流环运行转变为双环运行,电机的运行过程是这样吗?
使用了2812的定时器中断TI中断和T3中断,但是在程序运行过程中会奇怪的进入全比较中断4,但是在程序中全程没有使能全比较中断4,请问各位大神什么原因导致进入全比较中断4??如何解决这个问题?
程序由模板例程修改而来,全选择中断4程序部分是死循环,定时中断难以跳出,是不是哪里设置有问题,求大神帮助!!!!
使用28335进行计算一个很长的表达式赋值结果正确,但是将长式子拆为较短的式子之后,计算的结果就是正确的,这是怎么回事??
感谢各位TI工程和网友的帮助,我的电机终于转起来了。
接下来是调优部分,我对电机控制刚入门,有几个问题想请教:
1、运行lab5b,发现不太懂调pi,比如突然加个较大的负载,速度会立马掉下,然后再恢复平稳,那么我如何改善这个负载的瞬态特性?
2、运行lab5b,在低速下200-500,发现电机没力,加大负载电机会抖,会卡顿,会失步,那这是什么原因?如何优化?
目前暂时有这些疑惑,感谢帮忙解答